EDA tools support the addition of DFT logic to an IC design to add testability features to the IC design. Traditionally, the EDA design flow and associated EDA tools have focused on adding the DFT logic to the IC design after the IC design is translated into a gate level netlist.
However, because the gate level netlist is a relatively low level representation of the IC design, the functionality of the IC design for the DFT logic and the original logic under test is relatively obscured. As a result, an EDA user has increased difficulty in debugging any simulation issues. Also, netlist simulation is much slower than RTL simulation—anywhere from 2× to 30× slower based on the extent of transformations from netlist to RTL. Also, some DFT logic at RTL helps in functional test and allows for better integration of the IC design with the designed system.
Existing approaches that insert DFT logic at RTL insert a wrapper to connect the DFT logic at RTL. Such approaches modify the original hierarchy of the original design under test and create new ports. The result complicates equivalence checking and debugging by making it difficult to compare the original design under test and the design under test subsequent to inserting DFT logic.